Use Multiple Cores in Your General Packet Processing Model to Enhance Performance

In general, packet processing applications follow a standard regimen:

  •     Receive a packet (Rx)
  •     Process a packet (Proc)
  •     Transmit a packet (Tx)

The Rx part is, more or less, the same regardless of the type of packet processing. The Proc part is the heart of the application.

Use multiple cores in your general packet processing model to enhance performance fig b

This could be an Ethernet Switching application, an IP Routing application, Deep Packet Inspection (DPI), or a protocol process such as DHCP.

In gateway applications (routing and switching) the Tx is usually a different interface than the Rx interface whereas with a protocol process the Tx is usually a response to the sender and therefore to the same interface as the Rx.

​The performance requirements vary from application to application, but a 1Gbps Ethernet can transport approximately 1.5 million packets per second, so the requirements could be very steep.

One approach to achieving high performance is to employ multiple cores. For Rx, this can be done by using a hardware capability called Receive Side Scaling (RSS). With RSS the Network Interface (NIC) can queue packets to different threads on different cores based on fields in the packet. For Proc, this can be done by breaking the processing into multiple tasks and creating a pipeline. (sidebar on pipeline processing). Tx usually requires very little processing so there is little motivation for partitioning it.

Use multiple cores in your general packet processing model to enhance performance fig b

By effectively using multiple cores, the packet processing performance of the system is greatly enhanced because the system is processing multiple packets simultaneously.

Based on the general packet processing model described here, we will next show how this model can be implemented using DPDK and XEN: Packet Processing with DPDK and XEN


Show Buttons
Hide Buttons